Spin-on dielectric layers have been widely used to meet the planarization requirement, preventing a depth focus problem from occurring in the succeeding lithography process, and thus the accuracy of photo-patterning is improved. The planarization of spin-on dielectric layer in general requires a thick dielectric layer to be spin coated, while the stress of the dielectric layer is increased with the increment of the spin coating thickness. A spin-on dielectric layer will crack if its thickness/stress is too large, resulting in a high leaking current, and thus the dielectric layer loses the insulation characteristic. In order to avoid these drawbacks, a dielectric material was spin coated twice to obtain a thicker dielectric layer. Further, a dielectric layer having a low dielectric constant in general suffers a poor thermal stability and anti-water penetration ability, and thus there is a need to develop a technique to form a dielectric layer having enhanced properties.
U.S. Pat. No. 6,294,832 discloses a semiconductor device having a structure of copper interconnect/barrier dielectric liner/low-K dielectric trench and its fabrication method, in which a barrier dielectric liner made of a nitrogen-containing liquid-phase-deposition (LPD) fluorosilicate glass (FSG) film is used to replace a barrier metal layer and an oxide liner.